"<pre>
module P2101A

title 'P2101A'

declarations

"Version 5: [09-FEB-09] Add support for all seven master sockets."

"Version 4: [05-FEB-09] Add serial receiver running on 200 MHz clock to"
"receive instructions and data over cable of arbitrary length. The SDO"
"and SDI communication is now fully-functional. But we have not yet added"
"the code to operate SAO, which requires adding duplicate states to the"
"serial controller state machine."

"Version 3: [02-FEB-09] We add the Serial Job Register, Serial Controller State"
"machine prototype, and other TCM registers. Add rudimentary Serial Interface"
"that transmits null instructions."

"Version 2: [27-JAN-09] We expand the RAM interface to include control by the"
"serial RCM interface."

"Version 2: [15-SEP-08] We implement transmission from sockets 1 and 2, and"
"reception on channel 8, where this prototype version of the firmware expects"
"there to be receivers where the TCM would usually have transmitters."

"Version 1: [12-SEP-08] Provides LWDAQ server functionality, except that it"
"executes no LWDAQ controller jobs. The status and job registers are always"
"zero, indicating !BUSY. The 4-MByte on-board static RAM is available via"
"the ram portal address."


"Identifiers"
id_byte=101;
firmware_version_number=5;
hardware_version_number=1;

"Monitor Pins"
SW1 pin 168; "Switch 1, RESET"
SW2 pin 172; "Switch 2, CONFIG"
TP1..TP3 pin 27,26,25 istype 'com'; "Test Points"
LED1..LED4 pin 173,171,170,169 istype 'com'; "Indicator LEDs"
!PRST pin 174; "Power-Up Reset"

"Clock Pins"
LCK pin 154; "Local Clock, CLK3, 50 MHz"
RCK pin 66; "Reference Clock, CLK1, 32.768 kHz"
CLK2 pin 70 istype 'com'; "To CLK2"
CK pin 68; "Master Clock, CLK2, 50 MHz."
FCK pin 156; "Fast Clock, CLK0, 200 MHz."
MCI pin 151 istype 'com'; "Multiplier Clock Input"
MS0 pin 158 istype 'com'; "Multiplier Set 0"
MS1 pin 152 istype 'com'; "Multiplier Set 1"
CKO pin 160 istype 'com'; "External Clock Output"
CKI pin 159; "External Clock Input"

"RCM4200 Relay Interface"
!DS pin 24; "Data Strobe, PE6"
!CW pin 20; "Control Write, PE3"
SCLKC pin 21; "Serial EEPROM Clock, PE7"
CA0..CA5 pin 17,14,18,15,19,16; "Control Address, PB2..PB7"
control_addr = [CA5..CA0]; 
CD0..CD7 pin 9,5,10,6,11,7,12,8 istype 'com'; "Control Data, PA0..PA7"
control_data = [CD7..CD0]; 
!ETH pin 23; "Ethernet Activity, /ETH"
!RRST pin 175 istype 'com'; "Relay Reset, /RST_IN"

"RAM Interface"
RCE1 pin 62 istype 'com'; "RAM 1 Chip Enable"
RCD1 pin 64 istype 'com'; "RAM 1 Chip Disable"
!ROE1 pin 80 istype 'com'; "RAM 1 Output Enable"
!RWR1 pin 63 istype 'com'; "RAM 1 Write"
RCE2 pin 35 istype 'com'; "RAM 2 Chip Enable"
RCD2 pin 34 istype 'com'; "RAM 2 Chip Disable"
!ROE2 pin 36 istype 'com'; "RAM 2 Output Enable"
!RWR2 pin 37 istype 'com'; "RAM 2 Write"
RA0..RA20 pin 71,72,73,74,75,85,84,83,82,81,51,50,
  49,48,47,57,58,59,60,61,52 istype 'com'; "RAM Address Bits"
ram_addr = [RA20..RA0];
RD0..RD7 pin 54,53,38,39,86,87,77,76 istype 'com'; "RAM Data Bits"
ram_data = [RD7..RD0];

"Raft Controller Module (RCM) Interface"
SCK1,SDO1,SAO1 pin 108,111,109 istype 'com'; 
  "Serial Clock, Serial Data Out, Synchronize, Channel 1"
SDI1 pin 112; "Serial Data In, Channel 1"
SCK2,SDO2,SAO2 pin 113,115,114 istype 'com'; 
  "Serial Clock, Serial Data Out, Synchronize, Channel 2"
SDI2 pin 116; "Serial Data In, Channel 2"
SCK3,SDO3,SAO3 pin 117,120,118 istype 'com'; 
  "Serial Clock, Serial Data Out, Synchronize, Channel 4"
SDI3 pin 121; "Serial Data In, Channel 4"
SCK4,SDO4,SAO4 pin 122,124,123 istype 'com'; 
  "Serial Clock, Serial Data Out, Synchronize, Channel 5"
SDI4 pin 125; "Serial Data In, Channel 5"
SCK5,SDO5,SAO5 pin 126,135,127 istype 'com'; 
  "Serial Clock, Serial Data Out, Synchronize, Channel 6"
SDI5 pin 136; "Serial Data In, Channel 6"
SCK6,SDO6,SAO6 pin 137,139,138 istype 'com'; 
  "Serial Clock, Serial Data Out, Synchronize, Channel 6"
SDI6 pin 140; "Serial Data In, Channel 6"
SCK7,SDO7,SAO7 pin 141,145,142 istype 'com'; 
  "Serial Clock, Serial Data Out, Synchronize, Channel 7"
SDI7 pin 146; "Serial Data In, Channel 7"

"Nodes and Sets"
BUSY node istype 'com,keep,pos'; "Busy with serial transfer"
CDS node istype 'reg'; "Control Data Strobe"
CONFIG node istype 'com'; "Configure"
DA0..DA21 node istype 'reg'; "Data Address"
data_addr = [DA21..DA0];
dab0=[DA7..DA0]; "data address byte zero"
dab1=[DA15..DA8]; "data address byte one"
dab2=[DA21..DA16]; "data address byte two"
DAC0 node istype 'com,keep'; "data address carry from byte zero"
DAC1 node istype 'com,keep'; "data address carry from byte one"
DASEL0..DASEL2 node istype 'com,keep'; "data address select"
DAI node istype 'reg,keep,pos'; "data address increment"
DRC node istype 'com,keep'; "decrement repeat counter"
RAMSEL node istype 'com,keep,pos'; "RAM Select"
RC0..RC23 node istype 'reg,keep'; "repeat counter"
rcb0=[RC7..RC0]; "repeat counter byte zero"
rcb1=[RC15..RC8]; "repeat counter byte one"
rcb2=[RC23..RC16]; "repeat counter byte two"
repeat_counter=[RC23..RC0]; "repeat counter"
RCZ node istype 'com,keep'; "repeat counter zero"
RCZ0 node istype 'com,keep'; "repeat counter zero in byte zero"
RCZ1 node istype 'com,keep'; "repeat counter zero in byte one"
RCZ2 node istype 'com,keep'; "repeat counter zero in byte two"
RCVD node istype 'reg'; "Receiving Data"
RCVI node istype 'reg'; "Receiving Instruction"
RESET node istype 'com'; "Reset"
RIR0..RIR7 node istype 'reg'; "Received Instruction Register"
rir = [RIR7..RIR0];
RSM8..RSM1 node istype 'reg,keep'; "receive select mask"
rsm = [RSM8..RSM1];
SAOFL node istype 'com'; "Serial Auxilliary Out Force LO"
SCJD node istype 'reg,keep';"serial controller job done"
SCRST node istype 'reg'; "serial controller reset"
SCS0..SCS5 node istype 'reg,pos,keep'; "serial controller state"
scs = [SCS5..SCS0];
SDR0..SDR7 node istype 'reg'; "Serial Data Register"
sdr = [SDR7..SDR0];
SDI node istype 'reg'; "Serial Data In"
SDOFL node istype 'com,pos,keep'; "Serial Data Out Force LO"
SDS node istype 'reg,pos'; "Serial Data Strobe"
SIR node istype 'com'; "Serial Instruction Ready"
SJR0..SJR3 node istype 'reg,keep'; "serial job register"
sjr = [SJR3..SJR0];
SRC node istype 'com'; "Shift Receive Counter"
SRS0..SRS3 node istype 'reg'; "Serial Receiver State"
srs = [SRS3..SRS0];
SRST node istype 'reg'; "Software Reset"
STA node istype 'com,pos,keep'; "Serial Transmitter Activate"
STD node istype 'com,keep'; "Serial Transmit Done"
STS0..STS3 node istype 'reg'; "Serial Transmit State"
sts = [STS3..STS0];
SW node istype 'com'; "Serial Write"
TDRSEL node istype 'com,keep'; "transmit data register select"
TDR7..TDR0 node istype 'reg,keep'; "transmit data register"
tdr = [TDR7..TDR0];
TSM8..TSM1 node istype 'reg,keep'; "transmit select mask"
tsm = [TSM8..TSM1];
SDR node istype 'com,pos,keep'; "Serial Data Ready"

"Address Locations"
id_addr=0; "hardware identifier (byte)"
rir_addr=2; "received instruction register"
sjr_addr=3; "serial job register (byte)"
tdr_addr=4; "transmit data register (byte)"
hv_addr=18; "hardware version number  (byte)"
fv_addr=19; "firmware version number (byte)"
da_addr=24; "data address (longint)"
cs_addr=40; "configuration switch (byte)"
srst_addr=41; "software reset (byte)"
tsm_addr=42; "transmit select mask (32 bits)"
rsm_addr=48; "receive select mask (32 bits)"
ram_portal_addr=63; "ram portal"

equations


"Clock Generator"
"---------------"

MS0 = 0;
MS1 = 0;
MCI = LCK;

CLK2 = LCK;

CKO=CK;


"Software and Hardware Reset"
"---------------------------"

"SRST is a bit we can set through the control bus. When we"
"set SRST, RESET becomes true. SRST returns to zero after"
"the write to the softare reset register is over."
SRST.clk=CK;
when (CDS & CW & (control_addr==srst_addr)) then SRST:=1;
else SRST:=0;

"We use RESET to reset all internal registers." 
RESET = (PRST # !SW1 # SRST);

"The CONFIG variable reflects the state of SW2."
CONFIG = !SW2;

"We drive the RCM4200 Reset line only when"
"we want to reset the RCM4200 Relay. Otherwise"
"we let it float. We must allow the Program Header"
"on the RCM4200 to drive the same line at other"
"times. We reset the relay on power-up and when we"
"press the reset switch, but not when the controller"
"receives a software reset at its software reset"
"address."
RRST.oe = (PRST # !SW1);
RRST = (PRST # !SW1);


"RCM4200 Relay Interface"
"-----------------------"

"Control Data Strobe arrives from the RCM interface. The"
"RCM module provides valid data during CDS on read cycles,"
"and expects valid data on the falling edge of CDS on write"
"cycles."
CDS.clk = CK;
CDS := DS;

"We drive the control data on read cycles only."
control_data.oe = !CW & CDS;


"Readback registers"
"------------------"

"Readback from the control address space is all zeros except"
"as specified below. In some cases, the zeros act as the valid"
"upper byte or upper nibble of a readback register."

"Serial Job Register"
when CDS & !CW & (control_addr==sjr_addr) then 
  control_data = [0,0,0,0,SJR3,SJR2,SJR1,SJR0];

"Hardware Identifier."
when CDS & !CW & (control_addr==id_addr) then
  control_data = id_byte;

"Firmware Version"
when CDS & !CW & (control_addr==fv_addr) then
  control_data = firmware_version_number;

"Hardware Version"
when CDS & !CW & (control_addr==hv_addr) then
  [CD1..CD0] = hardware_version_number;

"Configuration Switch"
when CDS & !CW & (control_addr==cs_addr) then
  [CD0] = !CONFIG;

"Received Instruction Register"
when CDS & !CW & (control_addr==rir_addr) then
  control_data = [RIR7..RIR0]; 

"RAM Portal"
when CDS & !CW & (control_addr==ram_portal_addr) then
  control_data = ram_data.pin; 


"Data Address"
"------------"

"We clock the data address on the rising edge of CK."
[dab0,dab1,dab2].clk = CK;
[dab0,dab1,dab2].aclr = RESET;

"The data address carry outputs simplify the counter logic."
DAC0 = (dab0==^hFF);
DAC1 = (dab1==^hFF);

"Data Address Increment is clocked by !CK. Any state machine"
"may assert it, but no state machine may unassert it. The"
"variable is unasserted when its state is unspecified, hence"
"the 'pos' directive in its node declaration. We increment"
"the data address by one on each rising edge of CK for which"
"we assert DAI."
DAI.clk = !CK;
when DAI then
{
  dab0 := dab0+1;
  when DAC0 then dab1 := dab1+1;
  else dab1 := dab1;
  when DAC1 & DAC0 then dab2 := dab2+1;
  else dab2 := dab2;
}

"We set the data address via the Control register interface. 
"We use the DASEL nodes to reduce the data address fan-in."
DASEL0 = CDS & CW & (control_addr==da_addr+3);
DASEL1 = CDS & CW & (control_addr==da_addr+2);
DASEL2 = CDS & CW & (control_addr==da_addr+1);

"We can write to the data address only when we are not"
"incrementing it."
when !DAI then
{
  when DASEL0 then dab0 := [CD7..CD0];
  else dab0 := dab0;
  when DASEL1 then dab1 := [CD7..CD0];
  else dab1 := dab1;
  when DASEL2 then dab2 := [CD5..CD0];
  else dab2 := dab2;    
}


"RAM Interface"
"-------------"

"We select the RAM on Serial Data Strobe with BUSY"
"or CDS and RAM portal access when !BUSY."
RAMSEL = 
     BUSY & SDS
  # !BUSY & CDS & (control_addr==ram_portal_addr);

"The RAM address is made up of the lower 21 bits"
"of the data address."
ram_addr = [DA20..DA0];

"We select RAM1 when DA21=0, and RAM2 when DA21=0."
"Here we're using the RAM disable lines, so RAM1"
"is selected by !DA21 (lower 2MBytes) and RAM2"
"is selected by DA21 (upper 2 MBytes).""
RCD1 = !DA21;
RCD2 = DA21;

"We use RAMSEL to enable the RAM chips. Note that they"
"will be enabled only when their RCD lines are unasserted."
RCE1 = RAMSEL;
RCE2 = RAMSEL;

"We route control data and ram data with SW and CW when"
"we have BUSY and !BUSY respectively."
RWR1 = BUSY & SW # !BUSY & CW;
RWR2 = BUSY & SW # !BUSY & CW;
ROE1 = BUSY & !SW & SDS # !BUSY & !CW & CDS;
ROE2 = BUSY & !SW & SDS # !BUSY & !CW & CDS;
ram_data.oe = RWR1 # RWR2;
when BUSY then ram_data = sdr;
else ram_data = control_data;

"We assert DAI for one clock period whenever we read"
"or write from RAM. We use the rca state machine to"
"detect the assertion of RAMSEL followed by un-assertion."
"At the end of the cycle, we assert DAI for one CK period"
"so that we increment the data address."
declarations
RCA0..RCA1 node istype 'reg'; "RAM Cycle Active"
rca = [RCA1..RCA0];
equations

rca.aclr = RESET;
rca.clk = CK;
state_diagram rca
  state 0: if RAMSEL then 1 else 0;
  state 1: if !RAMSEL then 2 else 1;
  state 2: goto 0;
equations 
when (rca == 2) then DAI := 1;


"Serial Job Register"
"-------------------"

declarations
idle_job=^d0;
write_job=1;
read_job=2;
abort_job=3;
reset_job=4;
execute_job=5;
null_job=6;
aux_write_job=9;
aux_read_job=10;
aux_abort_job=11;
aux_reset_job=12;
aux_execute_job=13;
aux_null_job=14;

null_inst=255;
equations

sjr.clk=CK;
sjr.aclr=RESET;
when SCJD then sjr:=idle_job;
else
{
  when CDS & CW & (control_addr==sjr_addr) then sjr:=[CD3..CD0];
  else sjr:=sjr;
}
BUSY=(sjr!=idle_job);


"Serial Controller"
"-----------------"

declarations
scs_rest=^d00;
scs_done=255;
scs_write_1=1;
scs_write_2=2;
scs_write_3=3;
scs_write_4=4;
scs_write_5=5;
scs_write_6=6;
scs_write_7=7;
scs_write_8=8;
scs_write_9=9;
scs_write_10=10;
scs_read_1=11;
scs_read_2=12;
scs_abort=14;
scs_reset=15;
scs_execute=16;
scs_null=17;
equations

"We reset the Serial Controller asynchronously by writing"
"to the job register at any time, or with the external reset"
"line."
SCRST.clk=!CK;
SCRST:=RESET # (CDS & CW & (control_addr==sjr_addr));

"We clock the Serial Controller State with CK."
scs.aclr=SCRST;
scs.clk=CK;

"The Serial Controller sits in its rest state until it"
"detects sjr!=idle`_job, whereupon it executes the job"
"specified by sjr. If at any time during this execution,"
"we write again to sjr, we will automatically reset the"
"Serial Controller to its rest state. Assuming the"
"controller completes the job, it moves to its scs_done"
"state, where it asserts SCJD."
state_diagram scs;

  state scs_rest: 
    case 
      sjr==idle_job:scs_rest;
      sjr==write_job:scs_write_1;
      sjr==read_job:scs_read_1;
      sjr==abort_job:scs_abort;
      sjr==reset_job:scs_reset;
      sjr==execute_job:scs_execute;
      sjr==null_job:scs_null;
      sjr>null_job:scs_rest;
    endcase;

  state scs_done:goto scs_rest;

  state scs_abort:
    if STD then scs_done;
    else scs_abort;

  state scs_reset:
    if STD then scs_done;
    else scs_reset;

  state scs_execute:
    if STD then scs_done;
    else scs_execute;

  state scs_null:
    if STD then scs_done;
    else scs_null;

  state scs_write_1:
    if STD then scs_write_2;
    else scs_write_1;

  state scs_write_2:
    if STD then scs_write_3;
    else scs_write_2;

  state scs_write_3:
    if STD then scs_write_4;
    else scs_write_3;

  state scs_write_4:
    if STD then scs_write_5;
    else scs_write_4;

  state scs_write_5:
    if STD then scs_write_6;
    else scs_write_5;

  state scs_write_6:
    if STD then scs_write_7;
    else scs_write_6;

  state scs_write_7:
    if STD then scs_write_8;
    else scs_write_7;

  state scs_write_8:
    if STD then scs_write_9;
    else scs_write_8;

  state scs_write_9:
    if STD & (sjr==write_job) then scs_write_10
    else if STD & (sjr==read_job) then scs_read_2
    else scs_write_9;

  state scs_write_10:
    if STD & RCZ then scs_done;
    else scs_write_10;

  state scs_read_1:
    if STD then scs_write_2;
    else scs_read_1;

  state scs_read_2:
    if RCZ then scs_done;
    else scs_read_2;
equations

when (scs==scs_abort) # (scs==scs_reset) 
  # (scs==scs_execute) # (scs==scs_null) 
  # (scs==scs_write_1) # (scs==scs_read_1) then STA = !STD;

when (scs>=scs_write_2) & (scs<=scs_write_9) then
  STA = TDRSEL;

when (scs>=scs_write_6) & (scs<=scs_write_9) then
  SRC = (sts==2);

SDS.clk=!CK;

when (scs==scs_write_10) then {
  SW = 0;
  SDS := (sts>=1) & (sts<=11);
  STA = !STD;
  DRC = (sts==11);
}

when (scs==scs_read_2) then {
  DRC = SDR;
  SDS := SDR;
  SW = 1;
}

SCJD.clk = !CK;
SCJD := (scs==scs_done);


"Transmit Data Register"
"----------------------"

TDRSEL = CDS & CW & (control_addr==tdr_addr);
tdr.clk = CK;
tdr.aclr = RESET;
when TDRSEL then tdr := control_data;
else tdr := tdr;


"Repeat Counter"
"--------------"

repeat_counter.clk=CK;
repeat_counter.aclr=RESET;

RCZ0=(rcb0==0);
RCZ1=(rcb1==0);
RCZ2=(rcb2==0);

RCZ=RCZ0 & RCZ1 & RCZ2;

"We decrement the repeat counter when DRC and the counter."
"is not zero. We shift new values into the repeat counter on"
"SRC."
when DRC & !RCZ then
{
  rcb0:=rcb0-1;
  when RCZ0 then rcb1:=rcb1-1;
  else rcb1:=rcb1;
  when RCZ0 & RCZ1 then rcb2:=rcb2-1;
  else rcb2:=rcb2;
} else {
  when SRC then {
    rcb0:=tdr;
    rcb1:=rcb0;
    rcb2:=rcb1;
  } else {
    repeat_counter:=repeat_counter;
  }
}


"Serial Transmitter"
"------------------"

sts.clk=!CK;
sts.aclr=RESET;
state_diagram sts;
  state 0:if STA then 1 else 0;
  state 1:goto 2; "0=start"
  state 2:goto 3; "1=data 0=instruction"
  state 3:goto 4; "data bit 7"
  state 4:goto 5;
  state 5:goto 6;
  state 6:goto 7;
  state 7:goto 8;
  state 8:goto 9;
  state 9:goto 10;
  state 10:goto 11; "data bit 0"
  state 11:goto 12; "1=stop"
  state 12:if !STA then 0 else 12;
equations

STD = (sts==12);

"Send abort instruction, code 3, bit stream: 00000000111"
when (scs==scs_abort) then {
  SDOFL = (sts>=1) & (sts<=8);
}

"Send reset instruction, code 4, bit stream: 00000001001"
when (scs==scs_reset) then {
  SDOFL = (sts>=1) & (sts<=7)
    # (sts>=9) & (sts<=10);
}

"Send execute instruction, code 5, bit stream: 00000001011"
when (scs==scs_execute) then {
  SDOFL = (sts>=1) & (sts<=7)
    # (sts>=9) & (sts<=9);
}

"Send null instruction, code 255, bit stream: 00111111111"
when (scs==scs_null) then {
  SDOFL = (sts>=1) & (sts<=2);
}

"Send write instruction, code 1, bit stream: 00000000011"
when (scs==scs_write_1) then {
  SDOFL = (sts>=1) & (sts<=9);
}

"Send read instruction, code 2, bit stream: 00000000101"
when (scs==scs_read_1) then {
  SDOFL = (sts>=1) & (sts<=8)
    # (sts==10);
}

"Send transmit data register, bit stream: 01xxxxxxxx1
when (scs>=scs_write_2) & (scs<=scs_write_9) then {
  SDOFL = (sts==1)
    # (sts==3) & !TDR7
    # (sts==4) & !TDR6
    # (sts==5) & !TDR5
    # (sts==6) & !TDR4
    # (sts==7) & !TDR3
    # (sts==8) & !TDR2
    # (sts==9) & !TDR1
    # (sts==10) & !TDR0
}

"Send ram data, bit stream: 01xxxxxxxx1
when (scs==scs_write_10) then {
  SDOFL = (sts==1)
    # (sts==3) & !RD7
    # (sts==4) & !RD6
    # (sts==5) & !RD5
    # (sts==6) & !RD4
    # (sts==7) & !RD3
    # (sts==8) & !RD2
    # (sts==9) & !RD1
    # (sts==10) & !RD0
}

SAOFL = RCK;



"Serial Receiver"
"---------------"

declarations
SSS0..SSS2 node istype 'reg'; "Serial Synchronizing State"
sss = [SSS2..SSS0];
SPM node istype 'com,keep'; "Serial Phase Match"
equations

sss.clk=!FCK;
srs.aclr=RESET;
state_diagram sss;
  state 0:if srs==1 then 1 else 0;
  state 1:goto 2;
  state 2:goto 3;
  state 3:goto 4;
  state 4:if srs==0 then 0 else 1;
equations;
SPM = (sss==4);

srs.clk=FCK;
srs.aclr=RESET;
state_diagram srs;
  state 0:if !SDI then 1 else 0; "wait for start bit LO"
  state 1:if SPM then 2 else 1; "1=data 0=instruction"
  state 2:if SPM then 3 else 2; "data bit 7"
  state 3:if SPM then 4 else 3; 
  state 4:if SPM then 5 else 4;
  state 5:if SPM then 6 else 5;
  state 6:if SPM then 7 else 6;
  state 7:if SPM then 8 else 7;
  state 8:if SPM then 9 else 8;
  state 9:if SPM then 10 else 9; "data bit 0"
  state 10: "1=stop, serial word ready"
    if SPM & SDI then 0;
    if SPM & !SDI then 11;
    if !SPM then 10;
  state 11: if SDI & SPM then 0 else 11; "waiting for stop bit"
equations

RCVD.clk=FCK;
RCVD.aclr=RESET;
state_diagram RCVD;
  state 0: 
    if (srs==1) & SDI & SPM then 1;
    else 0;

  state 1:
    if (srs==10) & SPM then 0;
    else 1;
equations

RCVI.clk=FCK;
RCVI.aclr=RESET;
state_diagram RCVI;
  state 0: 
    if (srs==1) & !SDI & SPM then 1;
    else 0;

  state 1:
    if (srs==10) & SPM then 0;
    else 1;
equations

SDR = (srs==10) & RCVD;
SIR = (srs==10) & RCVI;

sdr.clk=FCK;
sdr.aclr=RESET;
when (srs==0) then sdr:=sdr;
when (srs==1) then sdr:=0;
when (srs>=2) & (srs<=9) then {
  when SPM then [SDR7..SDR0] := [SDR6..SDR0,SDI];
  else sdr:=sdr;
}
when (srs==10) # (srs==11) then sdr:=sdr;
 
rir.clk=CK;
rir.ap=RESET;
when (scs==scs_done) then {
  rir:=null_inst;
} else {
  when SIR then rir:=sdr;
  else rir:=rir;
}


"Transmit Select"
"---------------"

tsm.clk = CK;
tsm.aclr = RESET;
when CDS & CW & (control_addr==tsm_addr+3) then tsm := control_data;
else tsm := tsm;

SCK1 = CK;
when TSM1 then {
  SDO1 = !SDOFL;
  SAO1 = !SAOFL;
} else {
  SDO1 = 1;
  SAO1 = 1;
}

SCK2 = CK;
when TSM2 then {
  SDO2 = !SDOFL;
  SAO2 = !SAOFL;
} else {
  SDO2 = 1;
  SAO2 = 1;
}

SCK3 = CK;
when TSM3 then {
  SDO3 = !SDOFL;
  SAO3 = !SAOFL;
} else {
  SDO3 = 1;
  SAO3 = 1;
}

SCK4 = CK;
when TSM4 then {
  SDO4 = !SDOFL;
  SAO4 = !SAOFL;
} else {
  SDO4 = 1;
  SAO4 = 1;
}

SCK5 = CK;
when TSM5 then {
  SDO5 = !SDOFL;
  SAO5 = !SAOFL;
} else {
  SDO5 = 1;
  SAO5 = 1;
}

SCK6 = CK;
when TSM6 then {
  SDO6 = !SDOFL;
  SAO6 = !SAOFL;
} else {
  SDO6 = 1;
  SAO6 = 1;
}

SCK7 = CK;
when TSM7 then {
  SDO7 = !SDOFL;
  SAO7 = !SAOFL;
} else {
  SDO7 = 1;
  SAO7 = 1;
}

rsm.clk = CK;
when CDS & CW & (control_addr==rsm_addr+3) then rsm := control_data;
else rsm := rsm;

SDI.clk = FCK;
SDI := (SDI1 # !RSM1) 
  & (SDI2 # !RSM2)
  & (SDI3 # !RSM3)
  & (SDI4 # !RSM4)
  & (SDI5 # !RSM5)
  & (SDI6 # !RSM6)
  & (SDI7 # !RSM7);



"Indicators Lamps"
"----------------"


LED1 = RCZ;
LED2 = SDS;
LED3 = (scs==scs_read_2) # (scs==scs_write_10);
LED4 = RESET & !CONFIG;


"Test Points"
"-----------"

TP1 = (srs>=1) & (srs<=2);
TP2 = (sts>=1) & (sts<=2);
TP3 = SDI;

end