library ieee;  
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity A2080 is 
    port (
        CLK40M,                  --40 MHz Clock input

        --RESETL,                  --Asynchronous reset

        A : in std_ulogic;        --LVDS signal in

        DACA,                    --DAC "A" bits
        DACB,                    --DAC "B" bits 

        LED                      --Green data LEDs

        : out std_logic_vector(7 downto 0);
             
        B,                       --LVDS return signal

        WAKE,                    --power switches

        EN5VREF,                 --5VREF enable
        EN0VREF,                 --0VREF enable  
        ENADC1,                  --ADC "1" enable
        ENADC2,                  --ADC "2" enable
		
		CLKEN,					 --clock enable

        LB,                      --Loop back

        LEDERR,                  --Red error signal LED

        TP1,
        TP2                      --Test pads

        : out std_logic;

        IO 

        : out std_logic_vector(15 downto 0));


    

--Opcode list

	constant wait_noop : integer := 0;

	constant ADC1_active : integer := 1;
	constant ADC2_active : integer := 2;

	constant DACA_active : integer := 5;
	constant DACB_active : integer := 6;

	--constant IO_low_in : integer := 9;
	--constant IO_high_in : integer := 10;

	constant IO_low_out : integer := 13;
	constant IO_high_out : integer := 14;

	constant LED_out : integer := 15;
	
end;

architecture main of A2080 is

    --signal RST : std_logic;      		-- reset pulse; currently unused
	
    signal synchronized_A : std_logic;  -- "A" synchronized to CLK40M
    
	signal synchronized_A_reg :         -- pipeline register of SA to create DA & DDA
     	 std_logic_vector(12 downto 0);
    
	signal delayed_A : std_logic;		-- "SA" positive edges delayed by 125 ns
    
	signal delayed_delayed_A : 			-- "SA" positive edges delayed by 250 ns
		std_logic;        	
		
	signal not_stop_bit : std_logic;	-- shows that command receiver is active
	
	signal driver_bit_register : 		-- pipeline register recording incoming bits
		std_logic_vector(16 downto 0);
	
	signal command_register :			-- 16 bit command word
		std_logic_vector(15 downto 0);
	
	signal address_register : 			-- 16 bit address word
		std_logic_vector(15 downto 0);
	
	signal command_strobe : std_logic;	-- loads data_bit_register into command_register		
	
	signal address_strobe : std_logic;	-- loads data_bit_register into address_register
	
	type state is (inactive, command_load, address_load, 
		data_transmit, command_receive, address_receive);

	signal current_state, next_state :  -- registers for current state, next state
		state;
		
	signal test_1 : std_logic; 			-- test signal
		
	alias SA : std_logic is synchronized_A;
	alias SA_reg : std_logic_vector (12 downto 0) is synchronized_A_reg;
	alias DA : std_logic is delayed_A;
	alias DDA : std_logic is delayed_delayed_A;
	
	begin
	
	
	
	CLKEN <= '1';
	    
		
	--command receiver is functional
	command_receiver: process (current_state) is begin
		command_strobe <= '0';
		address_strobe <= '0';
		command_register <= command_register;
		
		case current_state is
			when inactive =>
				if not_stop_bit = '1' then
					if SA = '1' then
						next_state <= command_receive;
					else 
						next_state <= address_receive;
					end if;
				else
					next_state <= inactive;
				end if;	
				command_strobe <= '0';
				address_strobe <= '0';
				
			when command_receive =>
				if not_stop_bit = '0' then
					next_state <= command_load;
				else
					next_state <= command_receive;
				end if;
				
			when address_receive =>
				if not_stop_bit = '1' then
					next_state <= address_load;
				else
					next_state <= address_receive;
				end if;
				
			when command_load =>
				command_register <= 
					driver_bit_register(16 downto 1);
				command_strobe <= '1';
				next_state <= inactive;
				
			when address_load =>
				address_register <= 
					driver_bit_register(16 downto 1);
				address_strobe <= '1';
				next_state <= inactive;
					
			when others =>
				next_state <= inactive;

		end case;
		
	end process;
		

	--signal update is functional
	signal_update: process (CLK40M) is begin
		if rising_edge(CLK40M) then
			SA <= not A; --remove not for versions after A208101A
            SA_reg <= SA_reg(11 downto 0) & SA;
            DA <= SA_reg(3) and not SA_reg(4);
            DDA <= SA_reg(8) and not SA_reg(9);    
			current_state <= next_state;
			if command_register(6) = '1' then 
				B <= not A; --remove not for versions after A208101A
			end if;
		end if;
	end process;   
	
	--not stop bit is functional
	receiver_active: process (CLK40M) is begin
		if rising_edge(CLK40M) then
			if (SA = '0' and DDA = '1') then 
				not_stop_bit <= '1';
			elsif (SA = '1' and DDA = '1') then
				not_stop_bit <= '0';
			else not_stop_bit <= not_stop_bit;
			end if;
		end if;
	end process;
				
	--driver bit register is functional with update to 17 bits
	driver_register_clock: process (DA) is begin
		if rising_edge(DA) then
			driver_bit_register <= 
				driver_bit_register(15 downto 0) & SA;
		else driver_bit_register <=
			driver_bit_register;
		end if;
	end process;
	

	IO(0) <= command_register(5);
	IO(1) <= '0';
	IO(2) <= command_register(4);
	IO(3) <= not command_register(12);
	IO(4) <= not command_register(13);
	IO(5) <= not command_register(15);
	IO(6) <= command_register(3);
	IO(8) <= command_register(2);
	IO(9) <= not command_register(9);
	IO(10) <= not command_register(10);
	IO(11) <= not command_register(11);
	IO(12) <= not command_register(14);
	IO(13) <= command_register(0);
	IO(14) <= command_register(1);
	
	LEDERR <= not_stop_bit;
		
	clock_output: process (CLK40M) is begin
	    IO(7) <= CLK40M;
	end process;
	
	WAKE <= command_register(7);
	LB <= command_register(6);
	TP2 <= '0';
	TP1 <= '0';
	ENADC1 <= '0';
	ENADC2 <= '0';
	EN0VREF <= '0';
	EN5VREF <= '0';
	DACB <= "00000000";
	DACA <= "00000000";
	
 
 end architecture main;