[Device]
Family = lc4k;
PartNumber = LC4256V-75T176C;
Package = 176TQFP;
PartType = LC4256V;
Speed = -7.5;
Operating_condition = COM;
Status = Production;
EN_PinGLB = yes;
EN_PinMacrocell = yes;

[Revision]
Parent = lc4k256v.lci;
DATE = 12/14/2009;
TIME = 15:37:55;
Source_Format = ABEL_Schematic;
Synthesis = Exemplar;

[Ignore Assignments]

[Clear Assignments]

[Backannotate Assignments]

[Global Constraints]

[Location Assignments]
layer = OFF;
LNK = pin,48,-,-,-;
ACT = pin,37,-,-,-;
LED1 = pin,5,-,-,-;
LED2 = pin,6,-,-,-;
LED3 = pin,7,-,-,-;
LED4 = pin,8,-,-,-;
CSW = pin,175,-,-,-;
TP1 = pin,9,-,-,-;
TP2 = pin,10,-,-,-;
TP3 = pin,11,-,-,-;
TP4 = pin,12,-,-,-;
TP5 = pin,14,-,-,-;
TP6 = pin,15,-,-,-;
TP7 = pin,16,-,-,-;
TP8 = pin,17,-,-,-;
CA0 = pin,62,-,-,-;
CA1 = pin,63,-,-,-;
CA2 = pin,60,-,-,-;
CA3 = pin,61,-,-,-;
CA4 = pin,58,-,-,-;
CA5 = pin,59,-,-,-;
RCD0 = pin,49,-,-,-;
RCD1 = pin,50,-,-,-;
RCD2 = pin,36,-,-,-;
RCD3 = pin,52,-,-,-;
RCD4 = pin,51,-,-,-;
RCD5 = pin,54,-,-,-;
RCD6 = pin,53,-,-,-;
RCD7 = pin,57,-,-,-;
CDSIN = pin,38,-,-,-;
CW = pin,35,-,-,-;
RESET = pin,161,-,-,-;
VA1 = pin,82,-,-,-;
VA2 = pin,84,-,-,-;
VA3 = pin,86,-,-,-;
VA4 = pin,93,-,-,-;
VA5 = pin,95,-,-,-;
VA6 = pin,97,-,-,-;
VA7 = pin,99,-,-,-;
VA8 = pin,81,-,-,-;
VA9 = pin,83,-,-,-;
VA10 = pin,85,-,-,-;
VA11 = pin,87,-,-,-;
VA12 = pin,94,-,-,-;
VA13 = pin,96,-,-,-;
VA14 = pin,98,-,-,-;
VA15 = pin,100,-,-,-;
VA16 = pin,103,-,-,-;
VA17 = pin,105,-,-,-;
VA18 = pin,107,-,-,-;
VA19 = pin,109,-,-,-;
VA20 = pin,112,-,-,-;
VA21 = pin,114,-,-,-;
VA22 = pin,116,-,-,-;
VA23 = pin,118,-,-,-;
VA24 = pin,77,-,-,-;
VA25 = pin,76,-,-,-;
VA26 = pin,75,-,-,-;
VA27 = pin,74,-,-,-;
VA28 = pin,73,-,-,-;
VA29 = pin,72,-,-,-;
VA30 = pin,71,-,-,-;
VA31 = pin,70,-,-,-;
DS0 = pin,117,-,-,-;
DS1 = pin,115,-,-,-;
AS = pin,80,-,-,-;
LWORD = pin,113,-,-,-;
IACK = pin,111,-,-,-;
VAM0 = pin,108,-,-,-;
VAM1 = pin,106,-,-,-;
VAM2 = pin,104,-,-,-;
VAM3 = pin,102,-,-,-;
VAM4 = pin,125,-,-,-;
VAM5 = pin,126,-,-,-;
WRITE = pin,127,-,-,-;
VD0 = pin,145,-,-,-;
VD1 = pin,141,-,-,-;
VD2 = pin,140,-,-,-;
VD3 = pin,139,-,-,-;
VD4 = pin,138,-,-,-;
VD5 = pin,137,-,-,-;
VD6 = pin,136,-,-,-;
VD7 = pin,135,-,-,-;
VDEN0 = pin,150,-,-,-;
VDEN1 = pin,142,-,-,-;
VDCK0 = pin,149,-,-,-;
VDCK1 = pin,147,-,-,-;
VDIR = pin,148,-,-,-;
AB = pin,123,-,-,-;
BA = pin,120,-,-,-;
ADIR = pin,121,-,-,-;
OE = pin,174,-,-,-;
ACLKAB = pin,124,-,-,-;
ACLKBA = pin,122,-,-,-;
FCK = pin,66,-,-,-;
CKOUT = pin,64,-,-,-;
CK = pin,68,-,-,-;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;

[Fitter Report Format]

[Power]

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]

[Netlist/Delay Format]

[IO Types]
layer = OFF;
LNK = LVCMOS33, PIN, 0, -;
ACT = LVCMOS33, PIN, 0, -;
LED1 = LVCMOS33, PIN, 0, -;
LED2 = LVCMOS33, PIN, 0, -;
LED3 = LVCMOS33, PIN, 0, -;
LED4 = LVCMOS33, PIN, 0, -;
CSW = LVCMOS33, PIN, 0, -;
TP1 = LVCMOS33, PIN, 0, -;
TP2 = LVCMOS33, PIN, 0, -;
TP3 = LVCMOS33, PIN, 0, -;
TP4 = LVCMOS33, PIN, 0, -;
TP5 = LVCMOS33, PIN, 0, -;
TP6 = LVCMOS33, PIN, 0, -;
TP7 = LVCMOS33, PIN, 0, -;
TP8 = LVCMOS33, PIN, 0, -;
CA0 = LVCMOS33, PIN, 0, -;
CA1 = LVCMOS33, PIN, 0, -;
CA2 = LVCMOS33, PIN, 0, -;
CA3 = LVCMOS33, PIN, 0, -;
CA4 = LVCMOS33, PIN, 0, -;
CA5 = LVCMOS33, PIN, 0, -;
RCD0 = LVCMOS33, PIN, 0, -;
RCD1 = LVCMOS33, PIN, 0, -;
RCD2 = LVCMOS33, PIN, 0, -;
RCD3 = LVCMOS33, PIN, 0, -;
RCD4 = LVCMOS33, PIN, 0, -;
RCD5 = LVCMOS33, PIN, 0, -;
RCD6 = LVCMOS33, PIN, 0, -;
RCD7 = LVCMOS33, PIN, 0, -;
CDSIN = LVCMOS33, PIN, 0, -;
CW = LVCMOS33, PIN, 0, -;
RESET = LVCMOS33, PIN, 0, -;
VA1 = LVCMOS33, PIN, 1, -;
VA2 = LVCMOS33, PIN, 1, -;
VA3 = LVCMOS33, PIN, 1, -;
VA4 = LVCMOS33, PIN, 1, -;
VA5 = LVCMOS33, PIN, 1, -;
VA6 = LVCMOS33, PIN, 1, -;
VA7 = LVCMOS33, PIN, 1, -;
VA8 = LVCMOS33, PIN, 1, -;
VA9 = LVCMOS33, PIN, 1, -;
VA10 = LVCMOS33, PIN, 1, -;
VA11 = LVCMOS33, PIN, 1, -;
VA12 = LVCMOS33, PIN, 1, -;
VA13 = LVCMOS33, PIN, 1, -;
VA14 = LVCMOS33, PIN, 1, -;
VA15 = LVCMOS33, PIN, 1, -;
VA16 = LVCMOS33, PIN, 1, -;
VA17 = LVCMOS33, PIN, 1, -;
VA18 = LVCMOS33, PIN, 1, -;
VA19 = LVCMOS33, PIN, 1, -;
VA20 = LVCMOS33, PIN, 1, -;
VA21 = LVCMOS33, PIN, 1, -;
VA22 = LVCMOS33, PIN, 1, -;
VA23 = LVCMOS33, PIN, 1, -;
VA24 = LVCMOS33, PIN, 1, -;
VA25 = LVCMOS33, PIN, 1, -;
VA26 = LVCMOS33, PIN, 1, -;
VA27 = LVCMOS33, PIN, 1, -;
VA28 = LVCMOS33, PIN, 1, -;
VA29 = LVCMOS33, PIN, 1, -;
VA30 = LVCMOS33, PIN, 1, -;
VA31 = LVCMOS33, PIN, 1, -;
DS0 = LVCMOS33, PIN, 1, -;
DS1 = LVCMOS33, PIN, 1, -;
AS = LVCMOS33, PIN, 1, -;
LWORD = LVCMOS33, PIN, 1, -;
IACK = LVCMOS33, PIN, 1, -;
VAM0 = LVCMOS33, PIN, 1, -;
VAM1 = LVCMOS33, PIN, 1, -;
VAM2 = LVCMOS33, PIN, 1, -;
VAM3 = LVCMOS33, PIN, 1, -;
VAM4 = LVCMOS33, PIN, 1, -;
VAM5 = LVCMOS33, PIN, 1, -;
WRITE = LVCMOS33, PIN, 1, -;
VD0 = LVCMOS33, PIN, 1, -;
VD1 = LVCMOS33, PIN, 1, -;
VD2 = LVCMOS33, PIN, 1, -;
VD3 = LVCMOS33, PIN, 1, -;
VD4 = LVCMOS33, PIN, 1, -;
VD5 = LVCMOS33, PIN, 1, -;
VD6 = LVCMOS33, PIN, 1, -;
VD7 = LVCMOS33, PIN, 1, -;
VDEN0 = LVCMOS33, PIN, 1, -;
VDEN1 = LVCMOS33, PIN, 1, -;
VDCK0 = LVCMOS33, PIN, 1, -;
VDCK1 = LVCMOS33, PIN, 1, -;
VDIR = LVCMOS33, PIN, 1, -;
AB = LVCMOS33, PIN, 1, -;
BA = LVCMOS33, PIN, 1, -;
ADIR = LVCMOS33, PIN, 1, -;
OE = LVCMOS33, PIN, 0, -;
ACLKAB = LVCMOS33, PIN, 1, -;
ACLKBA = LVCMOS33, PIN, 1, -;
FCK = LVCMOS33, PIN, 0, -;
CKOUT = LVCMOS33, PIN, 0, -;
CK = LVCMOS33, PIN, 1, -;

[Pullup]

[Slewrate]
SLOW = LED1, LED2, LED3, LED4, TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, RCD0, RCD1, 
	RCD2, RCD3, RCD4, RCD5, RCD6, RCD7, VA1, VA2, VA3, VA4, VA5, VA6, VA7, 
	VA8, VA9, VA10, VA11, VA12, VA13, VA14, VA15, VA16, VA17, VA18, VA19, VA20, 
	VA21, VA22, VA23, VA24, VA25, VA26, VA27, VA28, VA29, VA30, VA31, DS0, 
	DS1, AS, LWORD, IACK, VAM0, VAM1, VAM2, VAM3, VAM4, VAM5, WRITE, VD0, VD1, 
	VD2, VD3, VD4, VD5, VD6, VD7, VDEN0, VDEN1, VDCK0, VDCK1, VDIR, AB, BA, 
	ADIR, OE, ACLKAB, ACLKBA, CKOUT;

[Region]

[Timing Constraints]
layer = OFF;

[HSI Attributes]

[Input Delay]

[opt global constraints list]

[Explorer User Settings]

[Pin attributes list]

[global constraints list]

[Global Constraints Process Update]

[pin lock limitation]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[individual constraints list]

[Attributes list setting]

[Timing Analyzer]

[PLL Assignments]

[Dual Function Macrocell]

[Explorer Results]

[VHDL synplify constraints]

[VHDL spectrum constraints]

[verilog synplify constraints]

[verilog spectrum constraints]

[VHDL synplify constraints list]

[VHDL spectrum constraints list]

[verilog synplify constraints list]

[verilog spectrum constraints list]

[ORP Bypass]

[Register Powerup]

[Constraint Version]
version = 1.0;

[ORP ASSIGNMENTS]
layer = OFF;

[Node attribute]
layer = OFF;

[SYMBOL/MODULE attribute]
layer = OFF;

[Nodal Constraints]
layer = OFF;